The present invention relates to semiconductor devices and to their fabrication and, more particularly, to high-voltage transistors and to their fabrication in complimentary-metal-oxide-semiconductor (CMOS) devices.
Complex signal processing devices, such as digital signal processing devices, and the like, are used in numerous electronic devices, such as video processing modules, flat panel displays, inkjet printers and the like. The fabrication of such devices requires the integration of high-voltage transistors and low-voltage transistors in the same device. Additionally, since the signal processing devices are required to function at relatively low operational power, they are typically fabricated as CMOS devices. The integration of high-voltage transistors and low-voltage transistors is problematic because the two types of transistors widely differ in their geometric characteristics and operational ranges. For example, high-voltage transistors are required to transfer voltages at much higher levels than low-voltage transistors. High-voltage transistors typically handle about 10V or more, while low-voltage transistors are designed to operate at a supply voltage of less than 5V, typically about 1 to 3V. Accordingly, high-voltage transistors have gate lengths that can be an order of magnitude larger than low-voltage transistors. In the state-of-the-art devices, the low-voltage transistors are fabricated to have gate lengths in the sub-micron range.
Further complications arise in CMOS fabrication as a result of the requirement to fabricate both n-type and p-type transistors in the same device. The fabrication of transistors of different conductivity type requires the formation of well regions in the semiconductor substrate. Attention must be placed on the relative doping concentration levels to avoid performance degradation resulting from parasitic capacitance and the like.
In order to integrate the high-voltage transistors in device fabrication, manufacturers have explored the integration of both vertically-oriented and laterally-oriented transistor architecture. Lateral orientation offers the ability to access the terminals of the high-voltage transistors from the upper surface of the device. A diffused-metal-oxide-semiconductor (DMOS) structure, in which the channel region is laterally diffused underneath a gate electrode, into a region of opposite dopant type, is a common technique for fabricating a laterally-oriented, high-voltage transistor. The region into which the channel is diffused, called the drift region, becomes part of the MOS drain. The DMOS device supports a high voltage because the drift region is more lightly doped than the channel region; thus the voltage drop is spread across the wider drift region rather than the narrower channel region. The DMOS structure has the advantage of having a self-aligned gate in which the channel region is precisely aligned to the gate electrode. Although the DMOS structure can be fabricated to have precisely oriented components, the thermal processing required to diffuse the channel region is generally incompatible with the shallow junctions required to fabricate the low-voltage transistors.
In order to fabricate high-voltage transistors and avoid the thermal processing required for DMOS devices, laterally-oriented high-voltage transistors can also be fabricated by utilizing the well regions that support the CMOS device structure. In particular, an n-channel MOS (NMOS) high-voltage transistor can be fabricated using the p-well as the channel region of the device and the adjacent n-well as the drain/drift region of the device.
While avoiding the necessity of extensive thermal processing to diffuse the channel region, the use of well regions means that the high-voltage transistor cannot be fabricated with a self-aligned gate. Accordingly, the misalignment of the channel region to the gate is possible with the accompanying loss of device performance. To compensate for the potential misalignment of the channel region, the gate electrode can be fabricated to have larger dimensions. However, the increased size of the gate electrode requires a larger surface area for fabrication of the high-voltage transistor resulting in a undesirably large devices. Additionally, the utilization of a well region for device components is problematic in CMOS technology using compensated n-well structures, in which the n-well region is implanted into the p-well region. In these structures, the n-well has a higher doping concentration than the p-channel region; thus it is not an ideal drift region. Therefore, such structures are susceptible to avalanche breakdown during the voltage stressing experience by the well regions during operation of the high-voltage transistor. Additionally, excessively high substrate current can result from impact ionization at voltages near the avalanche limit of the device.
The demand for high performance complex devices requires that they be fabricated to have maximum operational efficiency and be readily integrated into a CMOS process. Additionally, to avoid the necessity of dramatically increasing the geometric dimensions of the device, the high-voltage transistors must not require vast increases in substrate area over that commonly required for low-voltage transistor fabrication. Accordingly, advances in high-voltage architecture and fabrication are necessary to achieve high performance devices compatible with sub micron CMOS technology.
In accordance with the invention, a process for fabricating a high-voltage transistor includes forming a gate dielectric layer on a substrate having a first region, in which an isolation region resides within the first region. A gate electrode is fabricated to overlie at least a portion of the first well region, a portion of the second well region and a portion of the isolation region. A channel region is formed beneath the gate electrode by implanting ions into the substrate using an edge of the gate electrode as an implantation mask. The ions are implanted at an angle of incidence that is offset from a normal of the substrate surface. An electrical contact is formed to the first region, where the electrical contact is separated from the channel region by the isolation region.
In another aspect of the invention a high-voltage transistor is provided that includes an isolation region residing within a doped region of a substrate. The isolation region has substantially vertical sidewalls. A gate electrode overlies a portion of the doped region and a portion of the isolation region and is separated from the substrate by a gate dielectric layer. A channel region underlies at least a portion of the gate electrode and is separated from the isolation region by a portion of the doped region.
In yet another aspect of the invention, a semiconductor device is provided having both a high-voltage transistor and a low-voltage transistor. The method of forming the channel region for the high-voltage transistor avoids excessive thermal processing, such that shallow junctions can be preserved in the low-voltage transistors. In particular, the junction depth of the channel region of the low-voltage transistor can be maintained at a design tolerance of less than about 50% of the junction depth of the source and drain regions of the low-voltage transistor.
The high-voltage transistor and fabrication process of the invention provide a fully self-aligned transistor architecture, while avoiding the extensive thermal processing found in the prior art. Additionally, the separation of the drain region from the channel region is achieved by using a high-density isolation process, such as shallow trench isolation, and results in the fabrication of a device having a relatively small substrate surface area. These and other advantages of the invention are fully set forth herein below.